CICADA: A New Tool to Design Circuits with Correction and Detection Abilities

Abstract

In view of rapid development of microelectronic industry, there is a growing need to ensure reliability and fault tolerance of combinational devices exposed to various destabilizing effects. To solve this problem, methods based on synthesis of concurrent error detection (CED) circuits are now increasingly used, which enable, at the expense of some structural redundancy, correcting and/or detecting errors arising in the circuit. For each specific circuit, depending on the chosen synthesis method, CED circuits have different reliability characteristics, which makes it difficult for designers to choose one or another architecture. Therefore, there is a need to increase automation level of the process of selecting a method for control circuit synthesis, depending on the initial parameters of the protected device. This work is devoted to development of methods and software for detecting the best method for synthesizing a control circuit, taking into account the user-introduced constraint on structural redundancy of the resulting circuit.