Choosing VLSI algorithms for finite field arithmetic

Abstract

The authors systematically synthesize finite field multipliers in VLSI using a well-known array synthesis technique which gives good estimates of area, latency, and period. The dependency graph (DG) is mapped to signal flow graphs (SFGs) using various projection and scheduling vectors which correspond to different multipliers in GF(2/sup m/). Previous work on arithmetic in GF(2/sup m/) suggests that a dual basis multiplier uses minimum area and a standard basis multiplier has a regular structure. On the contrary, the authors claim that standard basis and dual basis algorithms have basically the same DG structure and hence similar time and area in VLSI. They derive the DGs and SPGs to compare mesh and linear VLSI implementations of the algorithms and show how previous designs can be derived from them. They also show a DG for normal basis multiplication which requires large area because of a large XOR sum of products. They also explain the proper choice of finite field arithmetic algorithms by considering the higher level of algorithms in which they are embedded. >