Abstract
Power consumption is a key figure of merit for low data rate transceivers which are often used in autonomous battery operated devices. The use of forward error correction (FEC) schemes in such transceivers shall therefore not only be considered as a way to improve communication robustness but rather as a tradeoff between additional performance and power consumption overhead. In this paper, a selection method is described to size the parameters of a low power Reed-Solomon (RS) code. In a second step a FPGA implementation of the shortened RS(40,32,4) code over GF(28) is described. Several design improvements are investigated step by step, leading to a 61% global power reduction
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