Abstract

This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence Graphs, which distributes the computations of a C loop to Address-Generator Units and Processing Elements; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. The compiler was verified and analyzed using a cycle-accurate HiPReP simulation model.

Highlights

  • For several decades, architecture and compiler research in the domain of HighPerformance Computing (HPC) has concentrated on parallel manycore and multicore systems

  • The main contributions are (i) a Splitting Algorithm for Data Dependence Graphs (DDGs) that distributes the computations of a C loop to Address-Generator Units (AGUs) and to the Processing Elements (PEs) array; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing

  • Both architectures only handle integer operations, and there are no comparisons of mapping the same kernel to smaller and larger Coarse-Grained Reconfigurable Arrays (CGRAs) as we provide them

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Summary

Introduction

Architecture and compiler research in the domain of HighPerformance Computing (HPC) has concentrated on parallel manycore and multicore systems. The main contributions are (i) a Splitting Algorithm for Data Dependence Graphs (DDGs) that distributes the computations of a C loop to Address-Generator Units (AGUs) and to the PE array; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. Both the HiPReP hardware design and the accompanying compiler were developed in the HiPReP project [6].

CGRA Hardware Architectures
CGRA Compiler Technology
Electronic Design Automation Algorithms
Compilers for Statically Reconfigurable CGRAs
Compilers for Dynamically Reconfigurable CGRAs
CGRA Compiler Frameworks
HiPReP Hardware Architecture Template Overview
Array Architecture
Processing Element
CHiPReP Design and Implementation
LLVM Frontend
LLVM Optimizer
Data Dependence Graph Generation
LLVM Pass RGVs
CHiPReP Module Mapper
Ad-Hoc Cluster Placement
Internal Node Placement
Pipeline Balancing
PBR Optimization
Assembler Code Generation
AGU and Memory Image Generator
Results
Filter Kernels
Conclusions and Future Work
Full Text
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