Chipping Size Reduction on Ultra-Thin Wafers and Narrow Saw-Streets for Wafer Sawing Process

Abstract

Chipping is a big problem when it enters the guard ring or die active area, because the size of chipping is bigger than Defect-Free Zone (DFZ). Thus, the smaller of chipping size, the better the quality, but chipping free is the best [1]. At present, the selling price of semiconductor products (especially on the IC product) is not too expensive as before, while the size of the package is getting smaller and smaller with higher density. Many companies interested in ultra-thin wafers (i.e. very thin wafers having thicknesses less than 100μm [2]). And also interested in increasing die per wafer (DPW) to have a competitive product cost. This increases the difficulty in the wafer sawing process because increasing die per wafer causes a narrow width of the saw-street meaning that the size of DFZ will be very narrow [3]. For the factory in this case study, customers provide the new revision of ultra-thin wafers (50μm) with the width of saw-streets at 60μm. This is narrower than the width of the existing saw-streets (80μm), which means that the current condition of the sawing process might not be suitable for this narrow saw streets of ultra-thin wafers. As a result, the approach to remedy this situation is conducted under the Six Sigma approach.