Chemical-mechanical-polishing: a new method for fabricating low capacitance silicon field emitter arrays with small gate apertures

Abstract

We have demonstrated a new method for fabricating low capacitance silicon-on-post FEA structures based on chemical mechanical polishing and self-aligned silicide formation. The advantages of the new approach are: (1) The gate aperture diameter is approximately equal to the diameter of the lithographically defined cap, i.e the diameter of the tall post. In principle this is scalable down to about 0.8 /spl mu/m using optical lithography, e.g., using an i-line stepper. Using e-beam, holographic, or optical interference lithographies, this process is expected to result in aperture diameters less than 100nm. (2) The gate aperture diameter is independent of the height of the post. (3) The process incorporates LPCVD SiO, as an interelectrode insulator. This oxide has optimal electrical and mechanical properties. (4) The planarization process provides global planarization in that it can be used without significant changes for wafers having different column height FEAs. (5) Due to the self-aligned mask formation, no lithographic processes are needed to create the final gated field emitters.