Chemical Mechanical Planarization Processes in Cu Interconnects: Invention to Implementation

Abstract

Chemical mechanical planarization (CMP) is one of the most critical semiconductor process technologies that enabled the fabrication of Cu interconnects and helped to achieve the performance goals of modern microprocessor and memory chips. Cu interconnects were introduced at the 130 nm technology node with oxide ( k ≈ 4) as the dielectric material. Since then, It has been the industry standard and has been extended to 22 nm technology node with low-k /ultra low-k ( k < 3) materials as dielectrics. The relentless drive to improve processor performance accelerated the introduction of new materials along with simultaneous reduction in minimum wiring dimensions and increase in the number of interconnects levels. The aggressive interconnect scaling coupled with the necessity to introduce new materials resulted in several unique challenges for the CMP processes. This paper presents examples of the innovative approaches that were used in solving some of these problems.