Abstract

MEMS and other emerging applications such as planar photonic devices, display devices and advanced chip and wafer level packaging, require superior planarity of thin films in order to enable greater functionality. The only process technology shown to consistently deliver both global and local planarity is Chemical Mechanical Planarization (CMP). CMP was initially developed to meet the increasingly stringent planarity requirements of the integrated circuit (IC) industry and has since become the standard planarization process within the semiconductor industry. However, emerging applications share film characteristics that present planarization challenges quite different from the traditional IC applications, including: 1) much larger step heights and wider feature sizes, 2) thicker films, 3) multiple materials present within the same layer, and 4) large discrepancies in pattern densities and feature sizes. Due to these challenges, standard CMP process steps, alone, may not deliver the desired planarity. In this paper, other techniques in combination with standard CMP will be investigated as a means to meet stringent planarity requirements of MOEMS. These techniques include: (a) optimizing CMP slurry formulation for both material removal rate and material selectivity, (b) integrating various technologies such as additional etch steps, protective masks and lift-off processes to deliver a surface that is more complementary to CMP, and (c) developing a two-step CMP process with a bulk removal step followed by a soft landing step. A working example will also be presented to demonstrate the feasibility of the proposed methodology.

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