Abstract
One of the most significant and challenging process integration issues for high- k dielectrics is the replacement of poly-Si gates in CMOS devices with either dual metal gates, or a single mid-band gap metal. The issue is the stability of the metal gate/high- k gate dielectric interface with respect to post-deposition thermal processing. Ab initio quantum chemistry calculations address this issue, and two questions have been resolved, providing results that are consistent with the experiment. The interface between a metal gate electrode and a high gate electrode and oxide dielectric cannot be atomically abrupt after post-deposition thermal processing. Instead there must be a chemically-graded interfacial transition region that mitigates some of the benefits of replacing dual poly-Si gates by metals, except for gate-last processing. However, electrical stress and heating during device operation will be significant driving force atomic motion, and the formation of an interfacial transition region.
Published Version
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