Checkability of FPGA projects by power-dissipation

Abstract

The issue is devoted to development of a checkability of the circuits for digital components of instrumentation and control safety-related systems, which operate ob-jects of the increased risk, such as power grids and power plants, high-speed transport and aircraft. Importance of a checkability of the circuits for ensuring func-tional safety of systems and their components in the field of critical applications where the operating mode is divided into normal and an emergency is noted. In these conditions, there is a problem of the hidden faults which can be accumulated throughout the long normal mode and reduce fault tolerance of schemes in the most responsible emergency operation. The most studied logical form of a checkability of the digital circuits determines efficiency of on-line testing of the digital components. Need of further development of a checkability of the circuits out of limits of its logical form as it does not solve a problem of the common signals, such as signals of reset and synchronization signals is shown. The faults arising in chains of the common signals can remain hidden, by blocking schemes of on-line testing is able which demonstrates the correct functioning of on-line testing means. For the solution of this problem, development of a checkability of the digital components on the basis of the power-dissipation is offered. The formula for analytical assessment of a checkability of the circuits by the power-dissipation for FPGA projects is received. The experi-ments directed to studying of a checkability of the digital circuits by the power-dissipation for the iterative array multipliers implemented in FPGA projects with the help of a CAD of Quartus Prime 17.1 Lite Edition (Intel of FPGA) are made. By means of the PowerPlay Power Analyzer utility, values of the power-dissipation for all FPGA project and for its input/output system and also dynamic and static compo-nents of the power-dissipation in core are received. On these data obtained at vari-ous activity of the input signals, calculations of a checkability of the circuits for the power-dissipation of iterative array multipliers with various word size from 16 to 64 bits are executed.