Abstract
The advent of low-power design has created a need for a metric (Figure of Merit) that is convenient to use in technical communications as well as a design guide. This paper examines a few common metrics for evaluating low-power CMOS circuit design effectiveness. It identifies charge-delay product (Qt) as a convenient and balanced metric. This function has an optimum point offering a better criterion than other common metrics for circuits that have operating margins that depend on the circuit delays.
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