Charge trapping in metal-ferroelectric-insulator-semiconductor structure with SrBi2Ta2O9∕Al2O3∕SiO2 stack

Abstract

The charge trapping is studied in metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with SrBi2Ta2O9(SBT)∕Al2O3∕SiO2 gate stack by high-frequency and pulsed capacitance-voltage (CV) measurements. The ferroelectric polarization is observed by high-frequency CV. Under fast gate voltage sweep in pulsed CV, the delay of electron trapping detrapping in the buffer layer induces an opposite CV hysteresis direction than that of the ferroelectric polarization. For memory programming, the hole trapping in the gate stack limits the electric field in SBT. Furthermore, the electron trapping during stress induces serious threshold voltage instability as well as erratic memory read out. All these charge trapping problems are important for the practical application and reliability of the memory with MFIS structure.