Abstract
In this paper we investigate the drain stress behavior and charge trapping phenomena of GaN-based high electron mobility transistors (HEMTs). We fabricated GaN-on-Si MIS-HEMTs with different dielectric stacks in the gate and gate drain access region and performed interface characterization and stress measurements for slow traps analysis. Our results show a high dependency of the on-resistance increase on interfaces in the gate-drain access region. The dielectric interfaces near the channel play a significant role for long term high voltage stress and regeneration of the device.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
