Abstract
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs. The comparison between pulsed Id-Vg and conventional DC measurements reveals that the intrinsic characteristics of GaAs transistors absent of transient charging effects can be much better than what have been observed in DC based test. The electron trapping process is found to be faster than de-trapping process. The results suggest that suppressing charge trapping in gate dielectrics is critical to implement high performance and reliable III-V MOSFETs for digital logic applications in post- silicon era.
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