Charge Trapping and Stability of E-Mode p-gate GaN HEMTs Under Soft- and Hard- Switching Conditions

Abstract

This paper reports a detailed analysis of the performance and stability of E-mode GaN HEMTs under soft and hard switching conditions. We developed a novel on-wafer setup that controls the overlapping between the gate and drain pulses and, simultaneously, senses the current at the source. This allowed us to plot the instantaneous power, the switching I-V locus and evaluate the switching losses on wafer level. The dynamic on-resistance RDS,ON is evaluated during hard and soft switching at room temperature and high temperature. The results demonstrate that (i) the properties of the buffer impact on dynamic-Ron, in soft- and hard-switching; devices with non-optimized buffer have stronger dynamic-Ron under hard switching; (ii) Ron-increase under hard switching is not strongly influenced by switching (power) losses; (iii) results indicate that a higher dynamic-Ron in hard switching is correlated to a wider switching locus. The proposed testing approach can be used as a screening tool to evaluate – in one single measurement – the switching losses, the dynamic-Ron and the impact of hard-switching on wafer level.