Abstract

Abstract. This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.

Highlights

  • Fractional-N phase-locked loops (PLL) are widely used in radio frequency (RF) and high-speed digital applications

  • This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL)

  • As opposed to integer-N architecture they avoid the trade-off between low phase noise and fine frequency step, which makes them especially attractive for radar systems discussed by Pohl et al (2012), wireless sensor nodes as outlined by Ussmuller et al (2009) or wireless base stations, see Osmany et al (2013)

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Summary

Introduction

Fractional-N phase-locked loops (PLL) are widely used in radio frequency (RF) and high-speed digital applications. In integrated PLLs, the PD is usually composed of a phase-frequency detector (PFD) and a charge pump (CP). Unlike the topologies employing accumulators, the SDM shifts the quantization noise to frequency offsets above the loop bandwidth. This noise is folded down to low frequencies if the PD is nonlinear. This causes in-band phase noise and fractional spurs as discussed by De Muer and Steyaert (2003), Riley et al (2003), Pamarti et al (2004), Chien et al (2004), Arora et al (2005), and Hedayati and Bakkaloglu (2009). Since the investigated CP topologies suffer from a low output resistance, a low-noise voltage regulator is suggested in order to minimize the effect of supply noise

PLL architecture for a low phase noise
Linearity
Device noise
Power supply rejection ratio
Charge pump design
Phase detector linearity
Supply noise rejection
Performance comparison
Conclusions
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