Abstract
Optimized strategies for designing charge pumps having only capacitive loads are presented. The design strategies developed are with minimum silicon area, which is equivalent to that with minimum rise time, and with minimum power consumption. The approach allows designers to define the number of stages that minimize silicon area (and minimize rise time) or maximize power efficiency for a given input and output voltage. The approaches were analytically developed and validated through simulations and experimental measurements on 0.18-/spl mu/m EEPROM CMOS technology. Moreover, a detail comparison between the two design strategies is also carried out.
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