Abstract

New pixel detector concepts, based on commercial high voltage and/or high resistivity CMOS processes, are being investigated as a possible candidate to the inner and outer layers of the ATLAS Inner Tracker in the HL-LHC upgrade. A depleted monolithic active pixel sensor on thick film SOI technology is being extensively investigated for that purpose. This particular technology provides a double well structure, which shields the thin gate oxide transistors from the Buried Oxide (BOX). In addition, the distance between transistors and BOX is one order of magnitude bigger than conventional SOI technologies, making the technology promising against its main limitations, as radiation hardness or back gate effects. Its radiation hardness to Total Ionizing Dose (TID) and the absence of back gate effect up to 700 Mrad has been measured and published [1]. The process allows the use of high voltages (up to 300V) which are used to partially deplete the substrate. The process allows fabrication in higher resistivity, therefore a fully depleted substrate could be achieved after thinning. This article shows the results on charge collection properties of the silicon bulk below the BOX by different techniques, in a laboratory with radioactive sources and by edge Transient Current Technique, for unirradiated and irradiated samples.

Highlights

  • The XFAB thick film SOI technology is extensively investigated on monolithic prototype for the HL-LHC

  • The unexpected high leakage current before irradiation observed in the first version of the chip (XTB01) was corrected in the second prototype (XTB02) by slight changes in the process

  • XTB02 presents a factor of 10 less leakage current and an increase of the breakdown voltage to above 300 V is observed

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Summary

Thick film HV-SOI monolithic detector prototype

A new monolithic active pixel sensor built in 180 nm thick film SOI CMOS technology designed by the University of Bonn was fabricated using the XFAB process [7]. TID and absence of back gate effects were proven up to 700 Mrad [1] The process makes it possible to apply high bias voltages (up to 300V) which are used to partially deplete the substrate and to fabricate devices in higher resistivity (1 kΩ · cm) is possible. Either the output signal of a single pixel can be permanently monitored, or the full matrix can be read out using a rolling shutter with correlated double sampling Such a readout is too slow for an ATLAS application but is sufficient for the characterization of first prototypes. A new version, called XTB02, was designed by University of Bonn to investigate purely the charge collection properties of the silicon bulk bellow the BOX. The leakage current decreases by a factor of ten and the breakdown voltage increases from 150 V to above 300 V in prototype XTB02 for unirradiated samples

Charge collecting properties of the silicon bulk
Edge TCT measurements
Summary
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