Characterization of TLB and page allocation behavior on modern processors

Abstract

OF THE THESIS Characterization of TLB and Page Allocation Behavior on Modern Processors by Viswanathan Vaidyanathan Thesis Director: Dr.Abhishek Bhattacharjee Virtual memory support is prevalent in most modern processors and is facilitated through Translation Lookaside Buffers (TLBs) which play a major role in the overall system performance. TLB misses are costly since they require multiple high latency memory references to walk the page table and locate the desired Virtual Page Number (VPN) Physical Page Number (PPN) mapping. This study improves TLB hit rates by taking advantage of any contiguity present in the pages allocated by the Operating System (OS). By contiguity we refer to cases where consecutive VPNs are mapped to consecutive PPNs. Traditionally, OSs use large or superpages to collapse hundreds of such contiguous entries, thereby using one TLB entry to represent them rather than hundreds of entries they would normally require. Unfortunately due to implementation complexities superpaging has not been universally successful in reducing TLB pressure. We show, however, that even without explicit superpaging, various OS virtual memory allocation activities lead to intermediate levels of contiguity that may be exploited to coalesce