Characterization of the first prototype CMOS pixel sensor developed for the CEPC vertex detector

Abstract

CMOS pixel sensor has become extremely attractive for future high-performance tracking devices. It has been proposed for the vertex detector at the Circular Electron Positron Collider, which will allow precision measurements of the properties of the Higgs boson. To meet the stringent requirements for low power consumption, it is necessary to optimize the pixel sensor diode geometry to reach a high charge-over-capacitance ratio that allows reduction in analog power consumption. Collection electrode size and footprint are two critical elements in sensor diode geometry and have deciding impacts on the charge collection performance. A prototype CMOS pixel sensor, named JadePix-1, has been developed with pixel sectors implemented with different electrode sizes and footprints, and its charge collection performance has been characterized with radioactive sources. Charge-to-voltage conversion gains for pixel sectors under test have been calibrated with low-energy X-rays. Characterization results have been obtained for equivalent noise charge (below 10e−), charge collection efficiency (around 40%), charge-over-capacitance ratio (above 0.015 V) and signal-to-noise ratio (higher than 55). Small collection electrode size and large footprint are preferred to achieve high charge-over-capacitance ratio that promises low analog power consumption. Ongoing studies on sensor performance before and after irradiation, combined with this work, will conclude the diode geometry optimization.