Characterization of the charge trapping properties in p-channel silicon–oxide–nitride–oxide–silicon memory devices including SiO2/Si3N4 interfacial transition layer

Abstract

The role of SiO2/Si3N4 interfacial transition (IFT) layer in the oxide–nitride–oxide (ONO) tri-layer is quantitatively analyzed for the first time by simulating the temperature and stress-accelerated retention characteristics of p-channel silicon–oxide–nitride–oxide–silicon (SONOS) devices. The ONO tri-layer is modeled as an alloy-dielectric by changing the atomic concentration of silicon, oxygen and nitrogen. It is revealed that simulated results including the IFT layer are more consistent with the experimental data than those neglecting the IFT layer. In addition, the results show that the trapped charge density in IFT layer is two times larger than in the bulk Si3N4 film, due to the oxygen atoms penetrated from SiO2 cause the extrinsic defects in the IFT layer. The energy levels of the trapped charge are continuously distributed, and the peak value is ∼1.6 eV below the conduction band of the ONO tri-layer with a full width at half maximum of 0.45 eV.