Abstract
Interleaved power converters are used in high-current applications due to their inherent reduction of semiconductors stress and total ripple. Ripple reduction is accomplished by a correct phase shifting, and the filtering improvement explained by the increase in the ripple frequency. However, these benefits are wasted, among other reasons, by the mismatch of the phase inductor value. As a consequence, differences in the ripple amplitude among phases are produced, leading to a total current ripple significantly greater than the ideal case, the loss of the cancellation points and the generation of the switching frequency component and its harmonics. The works dealing with this subject matter have focused on particular cases, such as a given number of phases, a specific converter topology, or a particular case of inductance mismatch, disregarding a general analytical approach. This paper proposes an analytical method to characterize the total ripple in steady state as a function of the duty cycle and the number of phases under any condition on inductance mismatch. Experimental results validate the proposed method.
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