Abstract
Thinner gate oxide regions, less than 100Å wide, are needed as MOS devices are scaled down in size to improve performance and increase the number of devices per chip. Triple layer dielectrics, in which a Si3N4 film is embedded between two SiO2 layers, are being investigated since the nitride layer provides a better diffusion barrier against dopants, metals and impurities as well as higher effective dielectric constant than a single layer of SiO2. To minimise atom diffusion, low temperature growth techniques such as Remote Plasma Enhanced Chemical Vapour Deposition (RPECVD) are being considered. As low temperature growth is not an equilibrium process non-stochiometric compositions can be formed. The aim of this work is to investigate structural characterisation of these layers in cross section by TEM and compositional analysis by PEELS.Two oxide-nitride-oxide (ONO) structures, both with nominally 50Å of nitride sandwiched between 10Åoxide layers in one specimen (10-50-10), and 30Å oxide layers in the second specimen (30-50-30) were grown by RPECVD at Research Triangle Institute. Cross section TEM specimens were prepared in according to standard procedures.
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