Abstract
This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of guard ring contact in triple-well CMOS process. The deposited charge can induce parasitic bipolar amplification to broaden the transient widths between adjacent devices especially for the PMOS under the effects of potential gradient in deep N-well region.
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