Abstract
Motivated by the need for fast timing detectors to withstand up to 2 MGy of ionizing dose at the High Luminosity Large Hadron Collider, prototype low gain avalanche detectors (LGADs) have been fabricated in a single pad configuration, 2 × 2 arrays, and related p-i-n diodes, and exposed to Co-60 sources for study. Devices were fabricated with a range of dopant layer concentrations, and for the arrays, a variety of inter-pad distances and distances from the active area to the edge. Measurements of capacitance versus voltage and leakage current versus voltage have been made to compare pre- and post-irradiation characteristics in gain layer depletion voltage, full bulk depletion voltage, and breakdown voltage. Conclusions are drawn regarding the effects of the gammas on both surface and interface states and on their contribution to acceptor removal through non-ionizing energy loss from Compton electrons or photoelectrons. Comparison of the performances of members of the set of devices can be used to optimize gain layer parameters.
Highlights
The low gain avalanche detector (LGAD) [1–3], based on the planar technology, produces a signal in response to the generation of free carriers by a charged particle or high-energy photon; when operated, it is depleted by a reverse bias
The surface, gain layer, and bulk properties of the LGADs included in this study are found to change after gamma irradiation
LGADs have a much lower breakdown voltage than the p-i-n diodes, indicating that the LGAD breakdown occurs in the bulk at the electrode pad region
Summary
The low gain avalanche detector (LGAD) [1–3], based on the planar technology, produces a signal in response to the generation of free carriers by a charged particle or high-energy photon; when operated, it is depleted by a reverse bias. Systematic uncertainties include uncertainties associated with the setup configuration (typically 1.9%), the accuracy of the source and measurement instruments (±0.3% + 100 fA for the Keithley 237; ±0.029% + 300 pA for the Keithley 2410, and ±0.34% for the FIGURE 9 | Leakage current versus applied bias voltage, for quad devices taken from all wafers ( with four different initial values of the gain layer depletion voltage) These measurements were made at room temperature after application of 0.5 MGy, for the measurement configuration in which bias is applied to the back side of the chip, and leakage current is measured with ground connected to the guard ring plus 0, 1, 2, 3, or all 4 pads. Analyses of the measurements typically require linear fits, on which the uncertainty is typically a small percent
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