Characterization of Fine-Pitch Interconnections (≤ 10 μm) on Silicon Interconnect Fabric for Heterogeneous Integration

Abstract

Abstract We propose a fine-pitch, highly scalable, heterogeneous integration platform called the Silicon-Interconnect Fabric (Si-IF) where dielets are assembled with fine-pitch interconnects (≤ 10 μm) at short inter-dielet spacings (≤ 100 μm) using direct metal-metal Thermal Compression Bonding process (TCB). As a result, short links on Si-IF (≤ 500 μm) are used for inter-dielet communication, reducing the latency to ≤ 35 ps. We experimentally demonstrated the measured insertion loss in these short Si-IF links (≤ 500 μm) is ≤ 2 dB for frequencies up to 30 GHz. Consequently, we show that assemblies on Si-IF have 10–40X lower parasitic inductance, and 7–35X lower parasitic capacitance compared to assemblies on interposers and PCBs. We propose the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol for data transfer that efficiently utilizes the Si-IF to achieve data-rates of ≥ 10 Gbps/link at an energy/bit of ≤ 0.04 pJ/b. Further, the aggregate bandwidth/mm is ≥ 8 Tbps/mm. This corresponds to an improvement of 120–300X in bandwidth/mm and a reduction of 100–500X in energy/bit compared to conventional systems.