Characterization of epitaxial silicon layers made by reduced pressure/temperature CVD

Abstract

Abstract A rapid thermal processing (RTP) has been used to fabricate homoepitaxial layers of silicon at reduced pressure (1 to 10 Torr) and reduced temperature (800–900°C). Prior to deposition (the samples being chemically cleaned or used as-received) an “in situ” cleaning step is used at temperatures higher than the deposition temperature or at the same temperature as when using UV radiation. Results from both techniques are compared and discussed concerning residual doping concentration, defect density into the grown layers through Schottky diodes and DLTS measurements. Carrier concentration peaks are observed at the substrate/epitaxial layer interface and when the layers are grown by steps. These peak intensities are correlated with the “in situ” surface cleaning step and growth temperature. Spreading resistance measurements show the autodoping level which is very low even with highly doped p-type substrates. Mobility values are compared with bulk material values. TEM observations are also correlated with the electrical results. We observe that the type of defects generated at 800°C has a smalle r activation energy (and density) than that produced at 900°C. The former one is interpreted as corresponding to shallow impurities and the latter is considered as some type of structural defects. As a conclusion we show the feasibility of an “in situ” low temperature surface cleaning prior to deposition giving rise to results of comparable quality to those obtained using a high temperature cleaning.