Characterization of Al2O3/LaAlO3/SiO2 Gate Stack on 4H-SiC After Post-Deposition Annealing

Linhua Huang,Naoto Fujishima,Yong Liu,Xin Peng,Takashi Tsuji,Yuichi Onozawa,Johnny K O Sin,Chao Xiao,Yixiao Ding

doi:10.1109/ted.2021.3056024

Abstract

We fabricated Al 2 O 3 /LaAlO 3 /SiO 2 (ALS) gate stacks on 4H-SiC, with LaAlO 3 (LAO) film being annealed in O 2 atmosphere. The ALS gate stack annealed at 700 °C exhibits a much higher breakdown effective electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {eff}}$ </tex-math></inline-formula> ), which is approximately 1.8 times higher than that of traditional SiO 2 gate oxide. The ALS gate stack also yields a low interface state density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{\text {it}}$ </tex-math></inline-formula> ) thanks to the intact LAO film. However, an annealing temperature as high as 800 °C induced traps in the LAO film and deteriorated the SiO 2 –SiC interface. The 700 °C-annealed LAO film with a high dielectric constant ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> ) of 14 and a low trap density, coupled with good electrical characteristics, makes it a promising gate dielectric for SiC power metal-oxide-semiconductor (MOS) device applications.

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