Abstract
Herein, we apply theoretical models to characterize the transfer function and frequency response of a complex optoelectronic circuit that comprises a primary ultrafast sampling circuit followed by a cascade connection of N demultiplexing stages. The successive radio-frequency optoelectronic samplers were based on the cascade connection of positive-intrinsic-negative-photodiodes (PIN-PDs). We developed a procedure to calculate the principal design parameters that allows us to use optical power for each sampling and demultiplexing stage, such that the circuit can be designed based on the application requirements. The results obtained from the theoretical models were compared with the measurements obtained from the 2.5 GS/s sampling circuit connected in cascade with a 1.25 GS/s and a 625 MS/s demultiplexing circuit implemented using commercial PIN-PDs
Highlights
An optoelectronic switch implemented with a positive-intrinsic-negative-photodiode (PIN-PD) uses the resistance dependence of the optical power impinging on the PIN-PD to implement the switching function
The PIN-PD resistance value can be varied from approximately 100 kΩ to less than 1 Ω for a milliwatt change in the optical power across it
The procedure allows us to use the optical powers applied to each PIN-PD to design the sampling and demultiplexing circuit according to the application requirements
Summary
An optoelectronic switch implemented with a positive-intrinsic-negative-photodiode (PIN-PD) uses the resistance dependence of the optical power impinging on the PIN-PD to implement the switching function. If the sampled data rate exceeds the available processing speed of a single electronic quantizer, intermediate demultiplexing stages are required to demultiplex different phases of the sampled signal to yield a quantizer’s arrangement of low multichannel data rates. In this type of sampling scheme, the optical-to-electrical and electrical-to-optical transducers create. The procedure allows us to use the optical powers applied to each PIN-PD to design the sampling and demultiplexing circuit according to the application requirements. The results obtained from the theoretical models are compared with the measurements obtained from the 2.5 GS/s sampling circuit connected in cascade with a 1.25 GS/s circuit and a 625 MS/s demultiplexing circuit implemented using commercial PIN-PDs
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