Characterization of a 16-bit threshold logic single-electron technology adder

M Sulieman,V Beiu

doi:10.1109/iscas.2004.1328838

Characterization of a 16-bit threshold logic single-electron technology adder

M Sulieman, V Beiu

https://doi.org/10.1109/iscas.2004.1328838

Copy DOI

Publication Date: May 23, 2004

Citations: 40

Affiliation: Washington State University

#Single Electron Technology #Threshold-logic Gates + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

Single electron technology (SET) is one of the future technologies distinguished by its small and low-power devices. SET also provides simple and elegant solutions for threshold-logic gates (TLGs). This paper presents the design of an optimal TLG adder implemented in SET. This 16-bit Kogge-Stone style adder was fully designed and simulated using a Monte Carlo simulator. The simulation results give a quantitative estimate of both the delay and the power dissipation of the adder. The characteristics of our adder are compared with recent results estimating the energy-delay characteristics of advanced CMOS adders.

Full Text