Characterization of 4H- and 6H-Like Stacking Faults in Cross Section of 3C-SiC Epitaxial Layer by Room-Temperature μ-Photoluminescence and μ-Raman Analysis.

Viviana Scuderi,Ruggero Anzalone,Francesco La Via,Marco Mauceri,Cristiano Calabretta

doi:10.3390/ma13081837

Viviana Scuderi, Ruggero Anzalone + Show 3 more

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https://doi.org/10.3390/ma13081837

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Abstract

We report a comprehensive investigation on stacking faults (SFs) in the 3C-SiC cross-section epilayer. 3C-SiC growth was performed in a horizontal hot-wall chemical vapour deposition (CVD) reactor. After the growth (85 microns thick), the silicon substrate was completely melted inside the CVD chamber, obtaining free-standing 4 inch wafers. A structural characterization and distribution of SFs was performed by μ-Raman spectroscopy and room-temperature μ-photoluminescence. Two kinds of SFs, 4H-like and 6H-like, were identified near the removed silicon interface. Each kind of SFs shows a characteristic photoluminescence emission of the 4H-SiC and 6H-SiC located at 393 and 425 nm, respectively. 4H-like and 6H-like SFs show different distribution along film thickness. The reported results were discussed in relation with the experimental data and theoretical models present in the literature.

Highlights

Cubic silicon carbide (3C-SiC) is a very interesting material for high frequency and high power devices, owing to its wide band gap and its high speed of electron transport within the crystal [1,2]
The interface between 3C-SiC and Si is the origin of a high density of planar and volume defects, such as misfit dislocations, micro twins (MTs), anti-phase boundaries (APBs), and stacking faults (SFs) in the epilayer and voids in Si underneath the hetero-interface
3C-SiC growth was performed in a horizontal hot-wall chemical vapour deposition (CVD) reactor (ACIS M10 supplied by LPE) using (100)-oriented Si substrates

Summary

Introduction

Cubic silicon carbide (3C-SiC) is a very interesting material for high frequency and high power devices (sustainable energies, hybrid vehicles, low power loss inverters), owing to its wide band gap and its high speed of electron transport within the crystal [1,2]. Hetero-epitaxial growth of 3C-SiC on silicon (Si) substrate was developed because of the advantages of low cost and large size. It is difficult to obtain high quality 3C-SiC films [6] owing to the crystal lattice mismatch (20%) and the difference in thermal expansion coefficients (~23% at deposition temperatures and 8% at room temperature (RT)). They result in a large residual strain and in a poor crystallographic structure. The interface between 3C-SiC and Si is the origin of a high density of planar and volume defects, such as misfit dislocations, micro twins (MTs), anti-phase boundaries (APBs), and stacking faults (SFs) in the epilayer and voids in Si underneath the hetero-interface

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