Abstract
We investigate the reliability of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) in 55-nm technology under mixed-mode stress. We perform electrical characterization and implement a TCAD model calibrated on the measurement data to describe the increased base current degradation at different collector-base voltages. We introduce a simple and self-consistent simulation methodology that links the observed degradation trend to interface traps generation at the emitter/base spacer oxide ascribed to hot holes generated by impact ionization (II) in the collector/base depletion region. This effectively circumvents the limitations of commercial TCAD tools that do not allow II to be the driving force of the degradation. The approach accounts for self-heating and electric fields distribution allowing to reproduce measurement data including the deviation from the power-law behavior.
Highlights
SILICON Germanium (SiGe) Heterojunction Bipolar Transitors (HBTs) are currently the leading technology option for amplifiers for 5G networks and THz industrial sensors [1]–[3]
The devices analyzed in this study are state-of-the-art SiGe HBTs fabricated in 55-nm BiCMOS technology by STM [9]
We investigated the reliability of state-of-the-art SiGe HBTs in 55-nm technology under MM stress
Summary
SILICON Germanium (SiGe) Heterojunction Bipolar Transitors (HBTs) are currently the leading technology option for amplifiers for 5G networks and THz industrial sensors [1]–[3]. Surface states generation at the emitter-base (E-B) spacer oxide due to impinging hot carriers generated by impact ionization (II) [4]–[7] In earlier technologies such as the 0.13 μm process from IHP [4] and the first generation of the 55 nm process from STM [8], the base current degradation was reported to empirically follow a power-law. In the literature the physics of this mechanism was either only partially analyzed [5], [7], or explained by empirical [4] or approximated analysis [6] that are better suited for aging compact models to be used in circuit simulations than for TCAD aging models to be exploited for degradation-aware device optimization. The developed model gives a direct empirical connection between trap generation rate and II rate in contrast to earlier reports that either: i) computed the generation rate from hot carriers models [5] or from the energy distribution function of carriers [7]; or ii) derived an approximated analytical solution for the generated trap density with generation rates used as fitting parameters [6]
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