Characterization and performance comparison of the power DIMOS structure fabricated with a reduced thermal budget in 4H and 6H-SiC

Abstract

In this work, a reduced thermal budget processing scheme using aluminum as the p-well dopant is investigated for the fabrication of the power DIMOS (Double Implanted MOSFET) in 4H and 6H-SiC in an effort to improve the on-state conduction. The on-state conduction in 4H-SiC devices is limited severely by low values of carrier mobility at the surface as compared with 6H-SiC. Surface mobilities extracted on lateral MOSFETs indicate the mobility values in 6H-SiC (40 cm 2/Vs) are significantly higher than in 4H-SiC (5 cm 2/Vs). Therefore, even when step-bunching is avoided through the use of a reduced thermal budget, the intrinsic surface disorder in 4H-SiC is higher than in 6H-SiC and leads to degraded conduction at the surface. Moreover, mobility on accumulated surfaces is higher than on inverted surfaces in both polytypes. The relative insensitivity of surface mobility to gate bias and temperature changes does not conform to existing models for surface mobility necessitating the development of new models to explain carrier transport at implanted SiC surfaces. The present study suggests that unless the surface morphology of 4H-SiC is improved, the advantage of a higher vertical bulk mobility in 4H cannot be exploited and 6H will remain as the polytype of choice for the power DIMOS fabrication in SiC.