Characterization and optimization of a bipolar ESD-device by measurements and simulations

Abstract

The design of ESD (electro-static discharge) protection structures can be significantly shortened by using thermo-electrical device simulations. In many cases simulation results predict the performance of new designs enough accurate which makes it unnecessary to go through the whole manufacturing process of test chips. More important, however, they allow the designer to gain additional insight into a problem by examining device-internal parameters that are not obtainable through measurements, such as current densities, the electric field and the lattice temperature. In this article we investigate and optimize a p-base type npn-transistor with a vertical and a lateral operation mode. Based on the TCAD tool chain, we develop a methodology to simulate the transient switching behavior, the avalanche breakdown and the snapback holding voltages of the device. To validate our design methodology we implemented the evaluated devices on a real test chip which has also been used to gain the needed data for the calibration of the simulators. Thus we are able to compare simulation and measurements and found the simulated voltages to closely match values obtained in measurements. In addition we extracted a set of parameters for a compact circuit model describing the device under various ESD stress types.