Abstract
In this paper, tiny in-line defects which correlated with chip low yield were investigated. A procedure which has optimum use of FIBs with different function to prepare ultra-thin TEM sample to analyze tiny defects has been proposed, which help prepare overlap free TEM sample in tiny defect analysis process. TEM /EELS /EFTEM have been performed in tiny defect analysis. Two tiny in-line defect cases were studied, which were both found after poly gate etch but with different defect source.
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