Characteristics of transmission lines fabricated by CMOS process with deep n-well implantation

Abstract

We characterized the properties of transmission lines fabricated using a CMOS process with a deep n-well implantation and compared them with the properties of the transmission lines on the silicon substrate with other well formations, e.g., a p-well and those without well formations. The series inductance of the transmission line is nearly constant, for both the various well formations and the resistivities of the silicon substrate. The characteristic impedance of the transmission line on the silicon substrate with the deep n-well is higher than this value on the substrates with the p-well and those without well formations. This is because the capacitance of the transmission line on the silicon substrate with the deep n-well is larger due to the p-n junction. Moreover, the capacitance of the transmission line on the substrate with the deep n-well decreases when the dc bias voltage applied to the deep n-well is increased. The capacitance of the transmission line on the substrate with the deep n-well is nearly constant for the various resistivities of the silicon substrate, while the capacitance of the line on the substrate with the p-well decreases with higher resistivity of the substrate.