Abstract

The device described here comprises a p + substrate containing an epitaxial n-layer, on the surface of which is grown a thin (∼50 Å) tunnel oxide. A metal cathode is deposited on the oxide surface, and a metal anode on the back side of the p + substrate. A third terminal, the gate electrode, is connected to the n epilayer to provide for biasing the n- p + junction. The I-V characteristic exhibit two stable states: a high-impedance state and a low-impedance state which are separated by a negative-resistance region. The high-impedance state is stable for applied voltages up to the intrinsic threshold voltage, V s . When the switching voltage is exceeded, the device switches rapidly to the low-impendance state, which is characterized by a current that increases with little increase in the voltage across the device. The switching voltage may be reduced below V s by current or voltage biasing of the n- p + junction by means of the gate electrode. Gate efficiencies, the ratio of the change in switching voltage with d.c. gate voltage or current, of 10 V/V and 1.0 V/μA have been observed. Pulsed gate measurements are also presented, and it found that for pulse widths down to 0.1 μs the gate switching characteristics follow the d.c. characteristics. For pulse widths less than 0.1 μs the gate efficiencies are degraded. Suggestions for improving the device characteristics and the turn-on and turn-off time of the device and device reliability are discussed.

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