Characteristics of Thermally Nitrided Gate Oxide Grown on N- and P-type 4H-SiC Surface from Commercial SiC MOSFET Perspective

Abstract

In this paper, gate oxides on channel and JFET surface of silicon carbide (SiC) MOSFETs are comprehensively investigated on N-MOS and P-MOS capacitors based on an entire commercial planar gate SiC MOSFETs process. The Fowler-Nordheim (F-N) tunneling of gate oxide on the channel surface occurs at -15 V while that of JFET surface one happens at 25 V, which essentially results in the asymmetric maximum operating gate-source voltage (Vgs) of planar gate SiC MOSFETs. The charge-to-breakdown (QBD) of the gate oxide on the JFET surface is twenty-seven times higher than that of channel surface one, which suggests that the gate oxide on the channel surface is more susceptible to failure than that on the JFET surface. The density of interface traps (Dit) below the intrinsic Fermi level (Ei) is always higher than that above Ei. which could be the root cause of the subthreshold hysteresis of SiC MOSFETs. This paper helps deeply understand the significant issues of maximum operating negative Vgs and subthreshold hysteresis of commercial planar gate SiC MOSFETs.