Abstract
With the rapid development of microelectronics packaging and integration, the failure risk of micro-solder joints in packaging structure caused by impact load has been increasingly concerning. However, the failure mechanism and reliability performance of a Cu-pillar-based microbump joint can use little of the existing research on board-level solder joints as reference, due to the downscaling and joint structure evolution. In this study, to investigate the cracking behavior of microbump joints targeted at chip-on-chip (CoC) stacked interconnections, the CoC test samples were subjected to repeated drop tests to reveal the crack morphology. It was found that the crack causing the microbump failure first initiated at the interface between the intermetallic compound (IMC) layer and the solder, propagated along the interface for a certain length, and then deflected into the solder matrix. To further explore the crack propagation mechanism, stress intensity factor (SIF) of the crack tip at the interface between IMC and solder was calculated by contour integral method, and the effects of solder thickness and crack length were also quantitatively analyzed and combined with the crack deflection criterion. By combining the SIF with the fracture toughness of the solder–Ni interface and the solder matrix, a criterion for crack deflecting from the original propagating path was established, which can be used for prediction of critical crack length and deflection angle for the initiation of crack deflection. Finally, the relationship between solder thickness and critical deflection length and deflection angle of main crack was verified by a board level drop test, and the influence of grain structure in solder matrix on actual failure lifetime was briefly discussed.
Highlights
Three-dimensional (3D) integration of silicon dies or wafers has received considerable attention in the past decade, due to its advantages of higher I/O density, lower RC delay, capability of heterogeneous integration, and footprint shrinking
For ball grid array (BGA) level solder joints typically 200–500 μm in size, the main failure mode during drop impact loading is manifested as cracking along the interface of solder bump and the intermetallic compounds (IMCs) formed by soldering [3,4], and the joint at the outermost corner is found as the most critical, which fails along the solder–pad interface [5,6]
Recent research of drop reliability focuses on the 3D die-stacking structure. This includes the study by Chen et al who determined that the critical position under the board-level drop impact is the corner of bottom layer of copper via [8], and the reliability improvement with a thinner IMC layer was revealed by Hsien-Chie Cheng et al [9,10]
Summary
Three-dimensional (3D) integration of silicon dies or wafers has received considerable attention in the past decade, due to its advantages of higher I/O density, lower RC delay, capability of heterogeneous integration, and footprint shrinking. Recent research of drop reliability focuses on the 3D die-stacking structure This includes the study by Chen et al who determined that the critical position under the board-level drop impact is the corner of bottom layer of copper via [8], and the reliability improvement with a thinner IMC layer was revealed by Hsien-Chie Cheng et al [9,10]. We first observed the crack failure of a microbump joint in a chip-on-chip (CoC) test vehicle under drop test conditions and found that the crack formed at the edge of the soldering interface, propagated along the interface for a certain length, and deflected into the solder layer, eventually causing failure of the joint To elucidate this phenomenon, a finite-element model was constructed to investigate the crack propagation behavior, based on basic fracture mechanics theories. The experimental observations revealed how the grain structure of the solder layer may affect the actual cracking path and drop lifetime
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