Abstract
The size of the advanced Cu interconnects has been significantly reduced, reaching the current 7.0 nm node technology and below. With the relentless scaling-down of microelectronic devices, the advanced Cu interconnects thus requires an ultrathin and reliable diffusion barrier layer to prevent Cu diffusion into the surrounding dielectric. In this paper, amorphous carbon (a-C) layers of 0.75-2.5 nm thickness have been studied for use as copper diffusion barriers. The barrier performance and thermal stability of the a-C layers were evaluated by annealing Cu/SiO2/Si metal-oxide-semiconductor (MOS) samples with and without an a-C diffusion barrier at 400 °C for 10 h. Microstructure and elemental analysis performed by transmission electron microscopy (TEM) and secondary ion mass spectroscopy showed that no Cu diffusion into the SiO2 layer occurred in the presence of the a-C barrier layer. However, current density-electric field and capacitance-voltage measurements showed that 0.75 and 2.5 nm thick a-C barriers behave differently because of different microstructures being formed in each thickness after annealing. The presence of the 0.75 nm thick a-C barrier layer considerably improved the reliability of the fabricated MOS samples. In contrast, the reliability of MOS samples with a 2.5 nm thick a-C barrier was degraded by sp2 clustering and microstructural change from amorphous phase to nanocrystalline state during annealing. These results were confirmed by Raman spectroscopy, X-ray photoelectron spectroscopy and TEM analysis. This study provides evidence that an 0.75 nm thick a-C layer is a reliable diffusion barrier.
Published Version
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