Characteristics & Analysis of Instability Induced by Secondary Slow Trapping in Scaled CMOS Devices

Abstract

A new instability phenomenon in scaled CMOS devices has been observed. Threshold voltage shifts induced by this phenomenon in p and n-ch FETs are observed during negative bias stress when the gate electrode is negative biased with respect to the substrate. The shifts strongly depend on test temperature, bias conditions, and channel length of the devices. Although the shifts are in the same direction as those induced by slow trapping, the time and channel length dependence can not be explained by slow trapping. This paper describes the characteristics of this instability phenomenon and analytic experiments. We conclude that: 1) The threshold voltage shift caused by this phenomenon follows Arrhenius' law, and the activation energies for acceleration factors are 1.05 eV and the n-ch and 1.2 eV in the p-ch FETs. 2) The shift strongly depends on the passivation structures and the channel length of the device. 3) The shift recovery by annealing depends on annealing temperature, and the shift strongly depends on the baking treatment before the test. 4) The shift induced by the secondary slow trapping mechanism is due to the diffusion of something, probably moisture, initially involved in the phosphosilicate glass passivation layer.