Abstract
As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La2O3/Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La2O3/Si interface and the interface reactions at the W/La2O3 interface. The surface roughness effects are expected to be severe in future generations’ devices with even thinner gate dielectric film and smaller size of the devices.
Highlights
The continual downsizing process of CMOS devices has been slowed down in recent years due to difficulties encountered when approaching both physical and technological limits, which are believed to be of a couple of nanometers in feature size [1,2]
These limits are governed primarily by the available lithography techniques, and by the gate dielectric thickness in the sense of equivalent oxide thickness (EOT), which is limited by the thin layer deposition techniques and by some other processing steps that may result in the EOT
As device gate length being scaled to a few nanometers and the gate dielectric thickness approaching the atomic scale, it is expected that the thickness fluctuation of the gate dielectric, the surface roughness on the fins in the FinFET structure or on the nanowire in the Gate-All-Around (GAA) structure, the gate dielectric/silicon interface and the gate dielectric/metal gate interface could become comparable to the gate dielectric thickness itself [3,4]
Summary
The continual downsizing process of CMOS devices has been slowed down in recent years due to difficulties encountered when approaching both physical and technological limits, which are believed to be of a couple of nanometers in feature size [1,2]. As device gate length being scaled to a few nanometers and the gate dielectric thickness approaching the atomic scale, it is expected that the thickness fluctuation of the gate dielectric, the surface roughness on the fins in the FinFET structure or on the nanowire in the Gate-All-Around (GAA) structure, the gate dielectric/silicon interface and the gate dielectric/metal gate interface could become comparable to the gate dielectric thickness itself [3,4] They are basically non-scalable, and it results in the second group of technological limits which are the process and device variabilities, and it becomes the most critical issue for the yield and performance control of gigascale integrated circuit manufacturing [3,4,5]. The gate leakage current is the second technological issue arising from the surface roughness [4,5]
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