Characterisation of a new hump-free device structure for smart power and embedded memory technologies

Abstract

A new device structure suitable for smart power and embedded memory technologies is presented that provides ideal hump-free subthreshold behaviour for shallow trench isolations by locally thickening the gate dielectric. This device structure is compared with an alternative approach to remove the hump effect, an improved process that reduces the oxide recess of the isolating trench. The new device offers a superior subthreshold slope. Emphasis has been placed not only on the hump effect but also on the reliability characterisation. The gate integrity of the new structure is comparable and only a minor degradation of the hot-carrier lifetime is observed. The new device structure provides an easy way to remove the hump without any change in the process and is applicable to every technology that offers more than one gate dielectric.