Abstract
This chapter discusses the performance and architectural issues related to the networks. A network has either packet-multiplexed links or circuit-multiplexed links. Switch design and performance issues differ accordingly. Packet-multiplexed links terminating at a switch could be asynchronous, with no time slots and arbitrary packet lengths. The data plane functions in a packet switch are considered. These functions are performed on every packet and are thus high-volume, fast-timescale functions. The packet-processing capacity should minimize packet-processing delays even when the packet arrival rates are high. The packet arrival rate to the switch depends on the data rates on the links that the switch interconnects. The queueing delay and the loss probabilities in the input or the output queue are important performance measures for the switch and are a function of the switching capacity, the packet buffer sizes, and the packet arrival process. The control plane functions in a packet switch are slow-timescale functions and include functions such as executing the signaling protocols and evaluating the network state from the signaling messages exchanged. Time-slotted switches can switch variable-length packets by breaking a packet into small, fixed-length packets called cells and then switching the cells.
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