Chapter 9 Applications and CMP-Related Process Problems

Abstract

This chapter deals with the chemical–mechanical polishing (CMP)-related process problems in an integrated circuit (IC) manufacturing environment. The chemical–mechanical planarization (CMP) is one of the indispensable processes in the generations of transistor gate lengths equal to or smaller than 0.35μm. The chapter discusses various factors that play roles in the CMP nonuniformity problems, such as equipment and consumables, recipe parameters, and effect of the end effector. In addition to a tight distribution of the thickness variation within a wafer, the average of a group of individual thicknesses must also be targeted within a certain range. The variation of the mean from wafer to wafer is called “wafer-to-wafer nonuniformity” (WTWNU). Instability in polish rate and nonuniformity in tungsten CMP (W CMP) are also discussed in the chapter. They are attributable to the quantity of consumables and tool maintenance. However, their impact on products is not as direct as in oxide CMP, because the W CMP process is self-limited by the metal-oxide selectivity.