Chapter 8 VLSI network design

Abstract

Publisher Summary This chapter discusses VLSI design. The interaction between integrated circuit layout and combinatorial optimization is discussed. The viewpoint taken is that of a combinatorialist, which means that main emphasis is given to aspects of circuit layout that are theoretically well understood and/or belong currently to the most prominent combinatorial problems in circuit layout. The chapter discusses general layout problem. In this overall approach, the physical components of the chip are considered as given together with their interconnection structure, the so-called net lists. It aims at placing components and routing the nets simultaneously. The main optimization goal is to minimize the layout area. The routing phase which usually follows the placement is also discussed. In this phase, the physical components have already been placed, and the wiring between these components has to be laid out. The routing problem is usually divided into two subproblems, the layout problem and the layer assignment or wiring problem. The chapter deals with special layout technologies that usually occur in logic synthesis, i.e. in the construction of the physical components that are given for the layout and routing phases. This so-called linear layout method reveal some rich and surprising connections to independent and currently very active areas of graph theory such as graph searching, Robertson-Seymour theory, embedding graphs into interval graphs, and graph separation.