Abstract

Compilers translate high-level language source code into machine-specific assembly code. For this task, any compiler uses a model of the target processor. This model captures the compiler-relevant machine resources, including the instruction set, register files, and instruction scheduling constraints. While in traditional target-specific compilers a retargetable compiler uses an external processor model as an additional input that can be edited without the need to modify the compiler source code itself. This concept provides retargetable compilers with high flexibility with regard to the target processor. Retargetable compilers have been recognized as important tools in the context of embedded SoC design for several years. One reason is the trend toward increasing use of programmable processor cores as SoC platform building blocks that provide the necessary flexibility for fast adoption of, for example, new media encoding or protocol standards and easy (software-based) product upgrading and debugging. While assembly language was predominant in embedded processor programming for a long time, the increasing complexity of embedded application code now makes the use of high-level languages such as C and C++ just as inevitable as in desktop application programming. This chapter summarizes the state-of the art in retargetable compilers for embedded processors and outlines their design and use. It provides some compiler construction background to understand the different retargeting technologies and overviews some existing retargetable compiler systems. The chapter also describes the ways in which the “compiler/architecture co-design” concept can be implemented in a processor architecture exploration environment. The chapter concludes by taking a look at potential future developments in the area.

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