Chapter 4 - FPGA vs. ASIC Designs

Abstract

This chapter provides an overview of the significant differences between ASIC and FPGA design styles. When it comes to language-driven design flows, ASIC designers tend to write very portable code (in VHDL or Verilog) and to make the minimum use of instantiated (specifically named) cells. By comparison, FPGA designers are more likely to instantiate specific low-level cells. In the case of an ASIC, a group of gates can be placed close to each other such that their track delays are very small. This means that, depending on the design, ASIC engineers can sometimes be a little sloppy about this sort of thing. By comparison, if this sort of design were implemented on an FPGA with each of the gates implemented in a separate LUT, it would “fly like a brick” because the track delays on FPGAs are much more significant, relatively speaking. In reality, of course, a LUT can actually represent several levels of logic, so the position isn't quite as dire as it may seem at first. Having said this, the bottom line is that in order to bring up (or maintain) performance, FPGA designs tend to be more highly pipelined than their ASIC counterparts. This is facilitated by the fact that every FPGA logic cell tends to comprise both a LUT and a register, which makes registering the output very easy.