Abstract

This chapter discusses the Advanced Encryption Standard (AES) block cipher design, implementation tradeoffs, side channel hazards, and modes of use. The chapter provides only a cursory glance at the AES design, concentrating more on the key design elements important to implementers and how to exploit them in various tradeoff conditions. The AES block cipher accepts a 128-bit plaintext, and produces a 128-bit ciphertext under the control of a 128-, 192-, or 256-bit secret key. It is a Substitution-Permutation Network design with a single collection of steps called a round that are repeated 9, 11, or 13 times to map the plaintext to ciphertext. A single round of AES consists of four steps: (1) SubBytes, (2) ShiftRows, (3) MixColumns, and (4) AddRoundKey. The data cache side channel attack of Bernstein is presented in the chapter as a design hazard. The chapter concludes with the treatment of Cipher Block Chaining CBC and counter mode (CTR) modes of use for the AES cipher, specifically concentrating on what problems the modes are useful for, how to initialize them, and their respective use hazards.

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