Chapter 32 - Finite Difference Time Domain: A Case Study Using FPGAs

Abstract

This chapter presents a reconfigurable hardware accelerator that implements the finite difference time domain (FDTD) method. It presents the background, including applications of the FDTD method, and provides the analysis and design details of the field-programmable gate array (FPGA) accelerator for FDTD. Implementing the FDTD algorithm in hardware greatly increases its computational speed. The speedup is due to three major factors: fixed-point representation, custom memory interface design, and pipelining and parallelism. FDTD is a data-intense algorithm; the bottleneck of the hardware design is its memory interface. With the limited bandwidth between the FPGA and data memories, a carefully designed custom memory interface allows for full utilization of the memory bandwidth and greatly improves performance. The FDTD algorithm is also a computationally intense algorithm; by considering the tradeoffs between resources and performance, one has to implement as much pipelining and parallelism as possible to speed up the design. The FDTD algorithm is also a cellular automata, sharing a similar algorithmic structure with many other CA problems. The hardware design techniques and memory interface architecture presented in this chapter can be applied to a wide range of other CA problems to achieve speedup on an FPGA and to provide fast, small, low-power, and inexpensive implementations.